The invention relates to a method of manufacturing an insulated gate field-effect transistor in an entirely self-registering manner, in which a silicon body of which at least a surface-adjoining sub-region is of one conductivity type is provided with a number of surface zones of the second conductivity type while using a masking layer of a material different from silicon oxide which masks the underlying material of the semiconductor body against oxidation, from which zones the source and drain zone of the transistor are formed, and there is then provided, by means of an oxidation treatment, with an oxide pattern which is sunk in the silicon body at least over a part of its thickness and which extends above the surface zones and above the adjoining parts of the silicon body and which has a number of apertures which define mesa-shaped regions of the semiconductor body which form the channel region of the transistor and contact regions of the zones which in the mesa-shaped regions adjoin the surface of the body beside the sunken oxide pattern.
In manufacturing field-effect transistors it is conventional to provide the source and drain zones and the insulated gate electrode in a self-registering manner with respect to each other. In fact, such a process offers very important advantages; the transistors obtained in this manner can be small because only small alignment tolerances need be observed, while the high-frequency properties will generally be good as a result of the small stray overlap capacitances between the gate electrode and the source and drain zones.
In a very frequently used MOST process, the source and drain zones are diffused in the semiconductor body while using the gate electrode as a mask. The gate electrode usually consists of polycrystalline silicon.
However, this method has the disadvantage that the channel length of the transistor--the distance between the source and drain zones--is determined entirely by the precision with which a mask pattern can be copied in a photolacquer layer by means of the usual photoetching methods, and the accuracy with which the pattern in the photolacquer layer can then be etched in the polycrystalline material. This accuracy is often smaller than would be desired. In addition, these critical steps usually take place in a stage in which the surface of the semiconductor body is no longer flat but is strongly profiled as a result of the field oxide already provided around the active regions, which also restricts the smallest dimension which can be made in a reproducible manner.
U.S. Pat. No. 4,023,195 discloses an insulated gate field effect transistor in which the surface of the semiconductor body is covered with an oxide pattern which is sunk in the semiconductor body over a part of its thickness and which has apertures defining in the semiconductor body a number of mesas which form the channel region and contact regions of the source and drain zones of the transistor and in which the source and drain zones are situated entirely below the sunken oxide pattern except at the location of the mesas. Outside the channel region, the gate electrode may extend to above the sunken oxide pattern and to above the source and drain zones, since due to the thickness of the sunken oxide pattern the stray overlap capacitance between the source and drain zones on the one hand and the parts of the gate electrode situated on the sunken oxide pattern on the other hand are comparatively small. During the manufacture of this known transistor, the provision of the gate electrode will therefore require no critical alignment steps. On the contrary, the provision of the sunken oxide pattern according to the method described in this patent will require a critical alignment step with respect to the source and drain zones already provided in the semiconductor body, because the oxidation mask and the diffusion mask for which different masking layers are used are not self-registering. As a result of this, alignment tolerances must be observed in these known transistors which restricts the smallest dimension which can be made in a reproducible manner.
In particular when the transistor is of the n-conductivity type, in which the source and drain zones are of the n-type and the semiconductor body is of the p-type, it is desired to provide below the sunken oxide pattern beside the transistor a channel-stopping p-zone having a higher doping concentration than that of the semiconductor body so as to prevent parasitic channeling below the sunken oxide which, for example in the case in which the transistor forms part of an integrated circuit, can produce undesired connections between various circuit elements. In the manner described in the above-mentioned U.S. patent, such a channel stopping zone is obtained by means of implantation of a suitable impurity while using a separate photolacquer layer as an implantation mask. Often, however, it is desirable, both in connection with the simplicity of the process and in connection with the compactness of the semiconductor device to be manufactured, to also provide the channel-stopping zone in a self-registering manner with respect to the other zones to be provided.
A method in which the sunken oxide pattern and the source and drain zones are provided partially in a self-registering manner, namely in the direction from the source to the drain zone, by using the nitride layer masking against oxidation also as a doping mask, is disclosed in U.S. Pat. No. 4,043,848.
In this method, first windows are provided in the nitride layer via which windows doped zones are provided in the semiconductor body so as to obtain the source and drain zone of the transistor. After this doping step, the nitride layer is removed by etching to such an extent that only nitride spots remain above the channel region of the transistor and above the contact regions of the source and drain regions, after which the sunken oxide pattern is provided using said nitride spots as an oxidation mask by means of thermal oxidation.
Therefore, the nitride mask above the channel region is not fully self-registering with respect to the already-defined source and drain zone of the transistor, as it is not self-registering in the direction transverse to the current direction. Often, and in particular with very small dimensions and large packing densities, a complete self-registration would be desirable. Moreover, in this known process no channel-stopping zone is used. Such a channel-stopping zone is often desired and is preferably also provided in a self-registering manner with respect to the other parts to be provided of the devices to be manufactured.
A similar method in which, however, a channel-stopping zone is provided below the sunken oxide pattern is disclosed in Netherlands Patent Application No. 7704636 (laid open to public inspection). In this known method, first diffusion windows for the source and drain zone are formed in the nitride layer; then, after the diffusion treatment, a mask having an aperture surrounding said diffusion windows for the channel stopping zone is provided. This method is also non-self-registering.